Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
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For example, the modification of the Chip Select 0 (CS0) parameters, while fetching the code from a memory
connected on this CS0, may lead to unpredictable behavior.
Problem Fix/Workaround
The code used to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a
memory connected to another Chip Select
42.2.14 System Controller (SYSC)
42.2.14.1 SYSC: Possible event loss when reading RTT_SR
If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when the RTT_SR is read, the
corresponding bit might be cleared. This can lead to the loss of this event.
Problem Fix/Workaround
The software must handle an RTT event as interrupt and as the only source of the interrupt source level 1.
42.2.15 Two-wire Interface (TWI)
42.2.15.1 TWI: Clock Divider
The value of CLDIV x 2
CKDIV
must be less than or equal to 8191, the value of CHDIV x 2
CKDIV
must be less than or
equal to 8191·
Problem Fix/Workaround
None.
42.2.15.2 TWI: Disabling Does not Operate Correctly
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1.
Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
Problem Fix/Workaround
The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled
before disabling the TWI.
42.2.15.3 TWI: NACK Status Bit Lost
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection and the TXCOMP bit
rising in the TWI_SR, the NACK bit is not set.
Problem Fix/Workaround
The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as long as transmission
is not completed.
Note: TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of the TWI_SR.
42.2.15.4 TWI: Possible Receive Holding Register Corruption
When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the TWI_RHR is
corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor OVERRUN status bits are set
if this occurs.
Problem Fix/Workaround
The user must be sure that received data is read before transmitting any new data.
42.2.15.5 TWI: Software reset
When a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new
transfer in READ or WRITE mode.
Problem Fix/Workaround
None.