Datasheet

719
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
42.2.11.2 SSC: Periodic Transmission Limitations in Master Mode
If the Least Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not sent.
Problem Fix/Workaround
None.
42.2.11.3 SSC: Last RK Clock Cycle when RK Outputs a Clock During Data Transfer
When the SSC receiver is used with the following conditions:
 the internal clock divider is used (CKS = 0 and DIV different from 0)
 RK pin set as output and provides the clock during data transfer (CKO = 2)
 data sampled on RK falling edge (CKI = 0)
At the end of the data, the RK pin is set in high impedance which might be seen as an unexpected clock cycle.
Problem Fix/Workaround
Enable the pull-up on RK pin.
42.2.11.4 SSC: First RK Clock Cycle when RK Outputs a Clock During Data Transfer
When the SSC receiver is used with the following conditions:
 RX clock is divided clock (CKS = 0 and DIV different from 0)
 RK pin set as output and provides the clock during data transfer (CKO = 2)
 data sampled on RK falling edge (CKI = 0)
The first clock cycle time generated by the RK pin is equal to MCK/(2 x (value +1)).
Problem Fix/Workaround
None.
42.2.12 Shutdown Controller (SHDWC)
42.2.12.1 SHDWC: Boundary Scan Mode Outputs the 32 kHz clock
In boundary scan mode, the SHDN pin outputs the 32 kHz clock.
Problem/Fix Workaround
There is only one way to disable the 32 kHz clock on the SHDN pin.
In boundary scan mode, connect TST and JTAGSEL pins to VDDBU and set the SHDN pin to low level.
42.2.12.2 SHDWC: Bad Behavior of Shutdown Pin
SHDN signal may be driven to Low level voltage during device power-on. If only VDDBU is powered during boot
sequence (No VDDCORE), the SHDN signal may be driven to Low level voltage after a delay. This delay is linked
to the startup time of the slow clock selected by OSCSEL signal. If the SHDN pin is connected to the Enable pin
(EN) of the VDDCORE regulator, VDDCORE establishment does not occur and the system does not start.
Problem/Fix Workaround
1. VDDCORE must be established within the delay corresponding to the startup time of the slow clock selected
by OSCSEL.
Add a glue logic to latch the rising edge of the SHDN signal. The reset of the latch output (EN_REG) can be
connected to a PIO and used to enter the shutdown mode.
42.2.13 Static Memory Controller (SMC)
42.2.13.1 SMC: Chip Select Parameters Modification
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if
accesses are performed on this CS during the modification.