Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
718
42.2.10.7 SPI: Software Reset Must be Written Twice
If a software reset (SWRST in the SPI Control Register) is performed, the SPI may not work properly (the clock is
enabled before the chip select).
Problem Fix/Workaround
The field SPI_CR.SWRST needs to be written twice to be correctly set.
42.2.10.8 SPI: Bad Serial Clock Generation on 2nd Chip Select
Bad Serial clock generation on the 2nd chip select when SPI_CSRx.SCBR = 1, SPI_CSRx.CPOL = 1 and
SPI_CSRx.NCPHA = 0.
This occurs using SPI with the following conditions:
 Master Mode
 CPOL = 1 and NCPHA = 0
 Multiple chip selects are used with one transfer with SCBR (baud rate) = 1 (i.e., when serial clock frequency
equals the system clock frequency) and the other transfers set with SCBR are not equal to 1.
 Transmitting with the slowest chip select and then with the fastest one, then an additional pulse is
generated on output SPCK during the second transfer.
Problem Fix/Workaround
Do not use a multiple Chip Select configuration where at least one SPI_CSRx is configured with SCBR = 1 and the
others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with SCBR (baud rate) = 1, the issue does not appear.
42.2.11 Serial Synchronous Controller (SSC)
42.2.11.1 SSC: Transmitter Limitations in Slave Mode
If TK is programmed as input and TF is programmed as output and requested to be set to low/high during data
emission, the Frame Synchro is generated one bit clock period after the data start, one data bit is lost. This
problem does not exist when generating periodic synchro.
Problem Fix/Workaround
The data need to be delayed for one bit clock period with an external assembly.
In the following schematic, TD, TK and NRST are SAM9261 signals, TXD is the delayed data to connect to the
device.