Datasheet

717
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
Mobile SDRAM initialization must be performed in internal SRAM.
42.2.10 Serial Peripheral Interface (SPI)
42.2.10.1 SPI: Pulse Generation on SPCK
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as follows:
 The Baudrate is odd and different from 1.
 The Polarity is set to 1.
 The Phase is set to 0.
Problem Fix/Workaround
Do not use this configuration.
42.2.10.2 SPI: Bad PDC behavior when CSAAT = 1 and SCBR = 1
If the SPI2 is programmed with SPI_CSRx.CSAAT = 1, SPI_CSRx.SCBR (baud rate) = 1 and two transfers are
performed consecutively on the same slave with an IDLE state between them, the second data is sent twice.
Problem Fix/Workaround
None. Do not use the combination CSAAT = 1 and SCBR = 1.
42.2.10.3 SPI: LASTXFER (Last Transfer) Behavior
In FIXED Mode, with CSAAT bit set, and in “PDC mode” the Chip Select can rise depending on the data written in
the SPI_TDR when the TX_EMPTY flag is set. For example, if the PDC writes a ‘1’ in bit 24 (LASTXFER bit) of the
SPI_TDR, the Chip Select rises as soon as the TXEMPTY flag is set.
Problem Fix/Workaround
Use the CS in PIO mode when “PDC mode” is required and CS has to be maintained between transfers.
42.2.10.4 SPI: Chip Select and fixed mode
In FIXED Mode, if a transfer is performed through a PDC on a Chip Select different from the Chip Select 0, the
output spi_size sampled by the PDC will depend on the field SPI_CSR0.BITS, whatever the selected Chip select
is. For example if SPI_CSR0 is configured for a 10-bit transfer whereas the SPI_CSR1 is configured for an 8-bit
transfer, when a transfer is performed in Fixed mode through the PDC on Chip Select 1, the transfer is considered
as a halfword transfer.
Problem Fix/Workaround
If a PDC transfer has to be performed in 8 bits, on a Chip select y (y different from 0), the field SPI_CSR0.BITS
must be configured in 8 bits in the same way as the field BITS of the CSRy Register.
42.2.10.5 SPI: Baud rate set to 1
When SPI_CSRx.SCBR (baud rate) = 1 (i.e., when serial clock frequency equals the system clock frequency), and
when the field BITS (number of bits to be transmitted) equals an ODD value (in this case 9, 11, 13 or 15), an
additional pulse is generated on output SPCK. No problem occurs if BITS field equals 8, 10, 12, 14 or 16 and
SCBR (baud rate) = 1.
Problem Fix/Workaround
None.
42.2.10.6 SPI: Software Reset
If the Software reset command is performed at the same clock cycle as an event for TXRDY occurs, there is no
reset.
Problem Fix/Workaround
Perform another software reset.