Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
716
AREA TEST, CODE
INCLUDE AT91SAM9xxx.inc
EXPORT soft_user_reset
soft_user_reset
;disable IRQs
MRS r0, CPSR
ORR r0, r0, #0x80
MSR CPSR_c, r0
;change refresh rate to block all data accesses
LDR r0, =AT91C_SDRAMC_TR
LDR r1, =1
STR r1, [r0]
;prepare power down command
LDR r0, =AT91C_SDRAMC_LPR
LDR r1, =2
;prepare proc_reset and periph_reset
LDR r2, =AT91C_RSTC_RCR
LDR r3, =0xA5000005
;perform power down command
STR r1, [r0]
;perform proc_reset and periph_reset (in the ARM pipeline)
STR r3, [r2]
END
42.2.9 SDRAM Controller
42.2.9.1 SDRAM: SDCLK Clock active after reset
After a reset the SDRAM clock is always active leading in over consumption in the pad.
Problem Fix/Workaround
The following sequence allows to stop the SDRAM clock.
1. Set the bit LPCB to 01 (Self-refresh) in the SDRAMC Low Power Register.
2. Write 0 in the SDRAMC Mode Register and perform a dummy write in sdram to complete.
42.2.9.2 SDRAM: JEDEC Standard Compatibility
In the current configuration, SDCKE rises at the same time as SDCK, while exiting self-refresh mode. To be fully
compliant with the JEDEC standard, SDCK must be stable before the rising edge of SDCKE. This is not the case
in this product.
Problem Fix/Workaround
Use a fully JEDEC compliant SDRAM module.
42.2.9.3 SDRAM: Mobile SDRAM Device Initialization Constraint
Using Mobile SDRAM devices that need to have their DQMx level HIGH during the Mobile SDRAM device
initialization, may lead to data bus contention. Therefore, external memories on the same EBI must not be
accessed.
This does not apply to Mobile SDRAM devices whose DQMx level is “don’t care” during this phase.
Problem Fix/Workaround