Datasheet

713
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
None.
42.2.3.2 Boot ROM: UDP Pad Pull-up Enable
When SAM9261 boots on internal ROM (BMS = 1), the UDP pad pull-up is enabled by software. This can lead to
an enumeration error.
Problem Fix/Workaround
Disable UDP pad pull-up at the beginning of the boot program (ex: at91bootstrap).
42.2.3.3 Boot ROM: Code Size Limitation for DataFlash and Serial Flash Boot
The maximum downloadable code size, from DataFlash and Serial Flash, is limted to 64 Kbytes. That limitation
does not affect other memories or existing AT91SAM9 products.
Problem Fix/Workaround
A) Reduce first level bootloader code to 64 Kbytes to boot on a second level bootloader code if needed.
B) If not possible, use another memory for booting purpose such as NAND Flash, serial EEPROM or a SDCard
which do not have this limitation.
42.2.4 Bus Matrix
42.2.4.1 Bus Matrix: Problem with locked transfers261
Locked transfers are not correctly handled by the Bus Matrix and can lead to a system freeze up. This does not
concern ARM locked transfers.
Problem Fix/Workaround
Avoid other Bus Matrix masters locked transfers.
42.2.5 LCD
42.2.5.1 LCD: Screen shifting after a reset
When a FIFO underflow occurs, a reset of the LCD DMA and FIFO pointers is necessary.
If only LCD DMA pointers are reset (FIFO pointers not reset), the displayed image is shifted.
Problem Fix/Workaround
Apply the following sequence to correctly reset LCD DMA and FIFO pointers:
 LCD power off
 DMA disable
 Wait for DMABUSY
 DMA reset
 LCD power on
 DMA enable.
Powering LCD off, then powering LCD on, resets the FIFO pointers.
Disabling DMA, then enabling DMA, resets the DMA pointers.
42.2.5.2 LCD: Periodic bad pixels
LCD periodic bad pixels is due to mis-aligned DMA base address in frame buffer. LCD DMA performs bursts to
read memory. The LCD DMA bursts must not cross the 1-Kbyte AMBA boundary.
Problem Fix/Workaround
The LCD DMA burst size in 32-bit words is programmed by BRSTLN field in DMAFRMCFG register.
The LCD DMA Base Address is programmed in DMABADDR1 register.
The LCD DMA Base Address must be programmed with a value aligned onto LCD DMA burst size, e.g.:
BRSTLN = 15