Datasheet

709
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
42.1.15.2 TWI: Disabling Does not Operate Correctly
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1.
Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
Problem Fix/Workaround
The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled
before disabling the TWI.
42.1.15.3 TWI: NACK Status Bit Lost
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection and the TXCOMP bit
rising in the TWI_SR, the NACK bit is not set.
Problem Fix/Workaround
The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as long as transmission
is not completed.
Note: TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of the TWI_SR.
42.1.15.4 TWI: Possible Receive Holding Register Corruption
When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the TWI_RHR is
corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor OVERRUN status bits are set
if this occurs.
Problem Fix/Workaround
The user must be sure that received data is read before transmitting any new data.
42.1.15.5 TWI: Software reset
When a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new
transfer in READ or WRITE mode.
Problem Fix/Workaround
None.
42.1.15.6 TWI: STOP not generated
If the sequence described as follows occurs:
1. WRITE 1 or more bytes at a given address.
2. Send a STOP.
3. Wait for TXCOMP flag.
4. READ (or WRITE) 1 or more bytes at the same address.
then STOP is not generated.
The line will show: DADR BYTE 1, ..., BYTE n, NO STOP generated, BYTE 1, ..., BYTE n.
Problem Fix/Workaround
Insert a delay of one TWI clock period before step 4 in the sequence above.
42.1.16 UDP
42.1.16.1 UDP: Bad data in the first IN data stage
All or part of the data of the first IN data Stage are not transmitted.It may then be a Zero Length Packet. The CRC
is correct. So the HOST may only see that the size of the received data does not match the requested length. But
even if performed again, the control transfer will probably fail.
Problem Fix/Workaround
These Control transfers are mainly used at device configuration. After clearing RXSETUP, the software needs to
compute the setup transaction request before writing data into the FIFO if needed. This time is generally greater