Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
708
None.
42.1.12 Shutdown Controller (SHDWC)
42.1.12.1 SHDWC: Boundary Scan Mode Outputs the 32 kHz clock
In boundary scan mode, the SHDN pin outputs the 32 kHz clock.
Problem/Fix Workaround
There is only one way to disable the 32 kHz clock on the SHDN pin.
In boundary scan mode, connect TST and JTAGSEL pins to VDDBU and set the SHDN pin to low level.
42.1.12.2 SHDWC: Bad Behavior of Shutdown Pin
SHDN signal may be driven to Low level voltage during device power-on. If only VDDBU is powered during boot
sequence (No VDDCORE), the SHDN signal may be driven to Low level voltage after a delay. This delay is linked
to the startup time of the slow clock selected by OSCSEL signal. If the SHDN pin is connected to the Enable pin
(EN) of the VDDCORE regulator, VDDCORE establishment does not occur and the system does not start.
Problem/Fix Workaround
1. VDDCORE must be established within the delay corresponding to the startup time of the slow clock selected
by OSCSEL.
2. Add a glue logic to latch the rising edge of the SHDN signal. The reset of the latch output (EN_REG) can be
connected to a PIO and used to enter the shutdown mode.
42.1.13 Static Memory Controller (SMC)
42.1.13.1 SMC: Chip Select Parameters Modification
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if
accesses are performed on this CS during the modification.
For example, the modification of the Chip Select 0 (CS0) parameters, while fetching the code from a memory
connected on this CS0, may lead to unpredictable behavior.
Problem Fix/Workaround
The code used to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a
memory connected to another Chip Select
42.1.14 System Controller (SYSC)
42.1.14.1 SYSC: Possible event loss when reading RTT_SR
If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when the RTT_SR is read, the
corresponding bit might be cleared. This can lead to the loss of this event.
Problem Fix/Workaround
The software must handle an RTT event as interrupt and as the only source of the interrupt source level 1.
42.1.15 Two-wire Interface (TWI)
42.1.15.1 TWI: Clock Divider
The value of CLDIV x 2
CKDIV
must be less than or equal to 8191, the value of CHDIV x 2
CKDIV
must be less than or
equal to 8191.
Problem Fix/Workaround
None.