Datasheet

707
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
42.1.11 Serial Synchronous Controller (SSC)
42.1.11.1 SSC: Transmitter Limitations in Slave Mode
If TK is programmed as input and TF is programmed as output and requested to be set to low/high during data
emission, the Frame Synchro is generated one bit clock period after the data start, one data bit is lost. This
problem does not exist when generating periodic synchro.
Problem Fix/Workaround
The data need to be delayed for one bit clock period with an external assembly.
In the following schematic, TD, TK and NRST are SAM9261 signals, TXD is the delayed data to connect to the
device.
42.1.11.2 SSC: Periodic Transmission Limitations in Master Mode
If the Least Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not sent.
Problem Fix/Workaround
None.
42.1.11.3 SSC: Last RK Clock Cycle when RK Outputs a Clock During Data Transfer
When the SSC receiver is used with the following conditions:
 the internal clock divider is used (CKS = 0 and DIV different from 0)
 RK pin set as output and provides the clock during data transfer (CKO = 2)
 data sampled on RK falling edge (CKI = 0)
At the end of the data, the RK pin is set in high impedance which might be seen as an unexpected clock cycle.
Problem Fix/Workaround
Enable the pull-up on RK pin.
42.1.11.4 SSC: First RK Clock Cycle when RK Outputs a Clock During Data Transfer
When the SSC receiver is used with the following conditions:
 RX clock is divided clock (CKS = 0 and DIV different from 0)
 RK pin set as output and provides the clock during data transfer (CKO = 2)
 data sampled on RK falling edge (CKI = 0)
The first clock cycle time generated by the RK pin is equal to MCK/(2 x (value +1)).
Problem Fix/Workaround