Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
706
42.1.10.4 SPI: Chip Select and fixed mode
In FIXED Mode, if a transfer is performed through a PDC on a Chip Select different from the Chip Select 0, the
output spi_size sampled by the PDC will depend on the field SPI_CSR0.BITS, whatever the selected Chip Select
is. For example if SPI_CSR0 is configured for a 10-bit transfer whereas the SPI_CSR1 is configured for an 8-bit
transfer, when a transfer is performed in Fixed mode through the PDC on Chip Select 1, the transfer is considered
as a halfword transfer.
Problem Fix/Workaround
If a PDC transfer has to be performed in 8 bits, on a Chip select y (y different from 0), the field SPI_CSR0.BITS
must be configured in 8 bits in the same way as the field BITS of the CSRy Register.
42.1.10.5 SPI: Baud rate set to 1
When SPI_CSRx.SCBR (baud rate) = 1 (i.e., when serial clock frequency equals the system clock frequency), and
when the field BITS (number of bits to be transmitted) equals an ODD value (in this case 9, 11, 13 or 15), an
additional pulse is generated on output SPCK. No problem occurs if BITS field equals 8, 10, 12, 14 or 16 and
SCBR (baud rate) = 1.
Problem Fix/Workaround
None.
42.1.10.6 SPI: Software Reset
If the Software reset command is performed at the same clock cycle as an event for TXRDY occurs, there is no
reset.
Problem Fix/Workaround
Perform another software reset.
42.1.10.7 SPI: Software Reset Must be Written Twice
If a software reset (SWRST in the SPI Control Register) is performed, the SPI may not work properly (the clock is
enabled before the chip select).
Problem Fix/Workaround
The field SPI_CR.SWRST needs to be written twice to be correctly set.
42.1.10.8 SPI: Bad Serial Clock Generation on 2nd Chip Select
Bad Serial clock generation on the 2nd chip select when SSPI_CSRx.SCBR = 1, SPI_CSRx.CPOL = 1 and
SPI_CSRx.NCPHA = 0.
This occurs using SPI with the following conditions:
 Master Mode
 CPOL = 1 and NCPHA = 0
 Multiple chip selects are used with one transfer with SCBR (baud rate) = 1 (i.e., when serial clock frequency
equals the system clock frequency) and the other transfers set with SCBR are not equal to 1.
 Transmitting with the slowest chip select and then with the fastest one, then an additional pulse is
generated on output SPCK during the second transfer.
Problem Fix/Workaround
Do not use a multiple Chip Select configuration where at least one SPI_CSRx is configured with SCBR = 1 and the
others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with SCBR (baud rate) = 1, the issue does not appear.