Datasheet

705
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
42.1.9 SDRAM Controller
42.1.9.1 SDRAM: SDCLK Clock active after reset
After a reset the SDRAM clock is always active leading in over consumption in the pad.
Problem Fix/Workaround
The following sequence allows to stop the SDRAM clock.
1. Set the bit LPCB to 01 (Self-refresh) in the SDRAMC Low Power Register.
2. Write 0 in the SDRAMC Mode Register and perform a dummy write in sdram to complete.
42.1.9.2 SDRAM: JEDEC Standard Compatibility
In the current configuration, SDCKE rises at the same time as SDCK, while exiting self-refresh mode. To be fully
compliant with the JEDEC standard, SDCK must be stable before the rising edge of SDCKE. This is not the case
in this product.
Problem Fix/Workaround
Use a fully JEDEC compliant SDRAM module.
42.1.9.3 SDRAM: Mobile SDRAM Device Initialization Constraint
Using Mobile SDRAM devices that need to have their DQMx level HIGH during the Mobile SDRAM device
initialization, may lead to data bus contention. Therefore, external memories on the same EBI must not be
accessed.
This does not apply to Mobile SDRAM devices whose DQMx level is “don’t care” during this phase.
Problem Fix/Workaround
Mobile SDRAM initialization must be performed in internal SRAM.
42.1.10 Serial Peripheral Interface (SPI)
42.1.10.1 SPI: Pulse Generation on SPCK
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as follows:
 The Baudrate is odd and different from 1.
 The Polarity is set to 1.
 The Phase is set to 0.
Problem Fix/Workaround
Do not use this configuration.
42.1.10.2 SPI: Bad PDC behavior when CSAAT = 1 and SCBR = 1
If the SPI2 is programmed with SPI_CSRx.CSAAT = 1, SPI_CSRx.SCBR (baud rate) = 1 and two transfers are
performed consecutively on the same slave with an IDLE state between them, the second data is sent twice.
Problem Fix/Workaround
None. Do not use the combination CSAAT = 1 and SCBR = 1.
42.1.10.3 SPI: LASTXFER (Last Transfer) Behavior
In FIXED Mode, with CSAAT bit set, and in “PDC mode” the Chip Select can rise depending on the data written in
the SPI_TDR when the TX_EMPTY flag is set. For example, if the PDC writes a ‘1’ in bit 24 (LASTXFER bit) of the
SPI_TDR, the Chip Select rises as soon as the TXEMPTY flag is set.
Problem Fix/Workaround
Use the CS in PIO mode when “PDC mode” is required and CS has to be maintained between transfers.