Datasheet

703
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
42.1.6.4 MCI: STOP during a WRITE_MULTIPLE_BLOCK command
The WRITE_MULTIPLE_BLOCK with a transfer size (PDC) not a multiple of the block length is not stopped by the
STOP command.
Problem Fix/Workaround
Choose an appropriate size for the block length.
42.1.7 NTRST
42.1.7.1 NTRST: Device does not boot correctly due to powerup sequencing issue
The NTRST signal is powered by VDDIOP power supply (3.3V) and the ARM processor is powered by VDDCORE
power supply (1.2V).
During the powerup sequence, if VDDIOP power supply is not established whereas the VDDCORE Power On
Reset output is released, the NTRST signal is not correctly asserted. This leads to a bad reset of the Embedded
Trace Macrocell (ETM9). The ARM processor then enters debug state and the device does not boot correctly.
Problem Fix/Workaround
1. Connect NTRST pin to NRST pin to ensure that a correct powering sequence takes place in all cases.
2. Connect NTRST to GND if no debug capabilities are required.
42.1.8 Reset Controller (RSTC)
42.1.8.1 RSTC: Reset During SDRAM Accesses
When a user reset, watchdog reset, or software reset occurs during SDRAM read access, the SDRAM clock is
turned off while data are ready to be read on the data bus. The SDRAM maintains the data until the clock restarts.
If the user reset, watchdog reset, or software reset is programmed to assert a general reset, the data maintained
by the SDRAM leads to a data bus conflict and adversely affects the boot memories connected on the EBI:
 NAND Flash boot functionality, if the system boots out of internal ROM.
 NOR Flash boot, if the system boots on an external memory connected on the EBI CS0.
Problem Fix/Workaround
1. Avoid user reset, watchdog reset, or software reset to generate a system reset.
2. Trap the user reset, watchdog reset, or software reset with an interrupt.
In the interrupt routine, power down the SDRAM properly and perform Peripheral and Processor Reset with
software in assembler.
Example with libV3.
 The main code:
//user reset interrupt setting
// Configure AIC controller to handle System peripheral interrupts
AT91F_AIC_ConfigureIt (
AT91C_BASE_AIC, // AIC base address
AT91C_ID_SYS, // System peripheral ID
AT91C_AIC_PRIOR_HIGHEST, // Max priority
AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED, // Level sensitive
sysc_handler );
// Enable SYSC interrupt in AIC
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS);
*AT91C_RSTC_RMR = (0xA5<<24) | (0x4<<8) | AT91C_RSTC_URSTIEN;
 The C SYS handler: