Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
694
38.10.2 MCI
The PDC interface block controls all data routing between the external data bus, internal MMC/SD module data
bus, and internal system FIFO access through a dedicated state machine that monitors the status of FIFO content
(empty or full), FIFO address, and byte/block counters for the MMC/SD module (inner system) and the application
(user programming).
These timings are given for a 25 pF load, corresponding to one MMC/SD Card.
Figure 38-12. MCI Timing Diagram
Table 38-23. MCI Timings
Symbol ParameterMinMaxUnit
1/t
CLOCK
CLK frequency at Data transfer Mode (PP) 0 50 MHz
2 Input hold time 0.9 – ns
3 Input setup time 0.2 – ns
4 Output hold time 8.5 – ns
5 Output setup time t
CLOCK
- 2.1 – ns
Valid Data
Valid Data
Valid Data
Valid Data
Bus Clock
CMD_DAT Input
CMD_DAT Output
1
2 3
4
5
6