Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
692
Figure 38-7. MISO Capture in Master Mode
Figure 38-8. SPI Master mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0)
Figure 38-9. SPI Master mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1)
MISO
(slave answer)
SPCK
(generated
by the master)
MISO cannot be provided
before the edge
Bit N Bit N+1
0 < delay < SPI
0
or SPI
3
Bit N
Internal
shift register
Safe margin,
always > 0
Common sampling point
Device sampling point
t
p
Extended t
p
SPCK
MISO
MOSI
SPI
2
SPI
0
SPI
1
SPCK
MISO
MOSI
SPI
5
SPI
3
SPI
4