Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
688
Figure 38-5. SMC Signals for NRD and NWR Controlled Access
38.9 SDRAMC Timings
The timings that follow are given for a 10 pF load on SDCK and 50 pF on the databus.
NRD
NCS
D0 - D31
NWR
A2-A25
A0/A1/NBS[3:0]
SMC7
SMC19 SMC20
SMC43
SMC37
SMC42
SMC8
SMC1
SMC2
SMC23
SMC24
SMC32
SMC7
SMC8
SMC6
SMC5
SMC4
SMC3
SMC9
SMC41
SMC40
SMC39
SMC38
SMC45
SMC9
SMC6
SMC5
SMC4
SMC3
SMC33
SMC30
SMC29
SMC26
SMC25
SMC31
SMC44
Table 38-19. SDRAMC Clock Signal
Symbol Parameter
Max
Unit1.8V Supply 3.3V Supply
1/(t
CPSDCK
) SDRAM Controller Clock Frequency
MCK Maximum Clock Frequency (See Table 38-6, “Master
Clock Waveform Parameters”)
MHz
Table 38-20. SDRAM Signals
Symbol Parameter
Min
Unit1.8V Supply 3.3V Supply
SDRAMC
1
SDCKE High before SDCK Rising Edge t
CPSDCK
/2 - 0.8 t
CPSDCK
/2 - 0.8 ns
SDRAMC
2
SDCKE Low after SDCK Rising Edge t
CPSDCK
/2 - 0.3 t
CPSDCK
/2 - 0.4 ns
SDRAMC
3
SDCKE Low before SDCK Rising Edge t
CPSDCK
/2 - 0.4 t
CPSDCK
/2 - 0.2 ns
SDRAMC
4
SDCKE High after SDCK Rising Edge t
CPSDCK
/2 - 0.2 t
CPSDCK
/2 - 0.2 ns
SDRAMC
5
SDCS Low before SDCK Rising Edge t
CPSDCK
/2 - 1.5 t
CPSDCK
/2 - 1.2 ns
SDRAMC
6
SDCS High after SDCK Rising Edge t
CPSDCK
/2 - 0.3 t
CPSDCK
/2 - 0.3 ns
SDRAMC
7
RAS Low before SDCK Rising Edge t
CPSDCK
/2 - 0.4 t
CPSDCK
/2 - 0.2 ns
SDRAMC
8
RAS High after SDCK Rising Edge t
CPSDCK
/2 - 0.4 t
CPSDCK
/2 - 0.4 ns
SDRAMC
9
SDA10 Change before SDCK Rising Edge t
CPSDCK
/2 - 0.4 t
CPSDCK
/2 - 0.5 ns
SDRAMC
10
SDA10 Change after SDCK Rising Edge t
CPSDCK
/2 - 0.3 t
CPSDCK
/2 - 0.4 ns
SDRAMC
11
Address Change before SDCK Rising Edge t
CPSDCK
/2 - 3.6 t
CPSDCK
/2 - 3.7 ns
SDRAMC
12
Address Change after SDCK Rising Edge t
CPSDCK
/2 - 0.4 t
CPSDCK
/2 - 0.5 ns
SDRAMC
13
Bank Change before SDCK Rising Edge t
CPSDCK
/2 - 3.3 t
CPSDCK
/2 - 3.3 ns
SDRAMC
14
Bank Change after SDCK Rising Edge t
CPSDCK
/2 - 0.5 t
CPSDCK
/2 - 0.5 ns