Datasheet

631
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
Note: Ri = red pixel component ON. Gi = green pixel component ON. Bi = blue pixel component ON. ri = red pixel component OFF.
gi = green pixel component OFF. bi = blue pixel component OFF.
37.5.2.7 Shifter
The FIFO, Serializer, Palette and Dithering modules process one pixel at a time in monochrome mode and three
sub-pixels at a time in color mode (R,G,B components). This module packs the data according to the output
interface. This interface can be programmed in the DISTYPE, SCANMOD, and IFWIDTH fields of the LCDCON2
register.
The DISTYPE field selects between TFT, STN monochrome and STN color display. The SCANMODE field selects
between single and dual scan modes; in TFT mode, only single scan is supported. The IFWIDTH field configures
the width of the interface in STN mode: 4-bit (in single scan mode only), 8-bit and 16-bit (in dual scan mode only).
For a more detailed description of the fields, see “LCD Controller (LCDC) User Interface” on page 644.
For a more detailed description of the LCD Interface, see “LCD Interface” on page 636.
37.5.2.8 Timegen
The time generator block generates the control signals LCDDOTCK, LCDHSYNC, LCDVSYNC, LCDDEN, used
by the LCD module. This block is programmable in order to support different types of LCD modules and obtain the
output clock signals, which are derived from the LCDC Core clock.
The LCDDOTCK signal is used to clock the data into the LCD drivers' shift register. The data is sent through
LCDD[23:0] synchronized by default with LCDDOTCK falling edge (rising edge can be selected). The CLKVAL
field of LCDCON1 register controls the rate of this signal. The divisor can also be bypassed with the BYPASS bit in
the LCDCON1 register. In this case, the rate of LCDDOTCK is equal to the frequency of the LCDC Core clock. The
minimum period of the LCDDOTCK signal depends on the configuration. This information can be found in Table
37-10.
The LCDDOTCK signal has two different timings that are selected with the CLKMOD field of the LCDCON2
register:
 Always Active (used with TFT LCD Modules)
 Active only when data is available (used with STN LCD Modules)
N+2 green_data_1 1010 3 0110 LCDD[3] LCDD[3] g1
N+2 blue_data_1 1010 2 0110 LCDD[2] LCDD[2] B1
…… … … … … ……
Table 37-9. Dithering Algorithm for Color Mode (Continued)
Frame Signal Shadow Level Bit used Dithering Pattern 4-bit LCDD 8-bit LCDD Output
Table 37-10. Minimum LCDDOTCK Period in LCDC Core Clock Cycles
Configuration
LCDDOTCK PeriodDISTYPE SCAN IFWIDTH
TFT Single Not applicable 1
STN Mono Single 4 4
STN Mono Single 8 8
STN Mono Dual 8 8
STN Mono Dual 16 16
f
LCDDOTCK
f
LCDC_clock
2 CLKVAL×
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