Datasheet

629
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
37.5.2.6 Dithering
The dithering block is used to generate the shades of gray or color when the LCD Controller is used with an STN
LCD Module. It uses a time-based dithering algorithm and Frame Rate Control method.
The Frame Rate Control varies the duty cycle for which a given pixel is turned on, giving the display an
appearance of multiple shades. In order to reduce the flicker noise caused by turning on and off adjacent pixels at
the same time, a time-based dithering algorithm is used to vary the pattern of adjacent pixels every frame. This
algorithm is expressed in terms of Dithering Pattern registers (DP_i) and considers not only the pixel gray level
number, but also its horizontal coordinate.
Table 37-7 shows the correspondences between the gray levels and the duty cycle.
The duty cycles for gray levels 0 and 15 are 0 and 1, respectively.
The same DP_i register can be used for the pairs for which the sum of duty cycles is 1 (e.g., 1/7 and 6/7). The
dithering pattern for the first pair member is the inversion of the one for the second.
The DP_i registers contain a series of 4-bit patterns. The (3-m)
th
bit of the pattern determines if a pixel with
horizontal coordinate x = 4n + m (n is an integer and m ranges from 0 to 3) should be turned on or off in the current
frame. The operation is shown by the examples below.
Consider the pixels a, b, c and d with the horizontal coordinates 4*n+0, 4*n+1, 4*n+2 and 4*n+3, respectively. The
four pixels should be displayed in gray level 9 (duty cycle 3/5) so the register used is DP3_5 =”1010 0101 1010
0101 1111”.
The output sequence obtained in the data output for monochrome mode is shown in Table 37-8.
Table 37-7. Dithering Duty Cycle
Gray Level Duty Cycle Pattern Register
15 1 -
14 6/7 DP6_7
13 4/5 DP4_5
12 3/4 DP3_4
11 5/7 DP5_7
10 2/3 DP2_3
9 3/5 DP3_5
8 4/7 DP4_7
71/2~DP1_2
63/7~DP4_7
52/5~DP3_5
41/3~DP2_3
31/4~DP3_4
21/5~DP4_5
11/7~DP6_7
00-