Datasheet

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SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
Figure 37-2. Datapath Structure
This module transforms the data read from the memory into a format according to the LCD module used. It has
four different interfaces: the input interface, the output interface, the configuration interface and the control
interface.
 The input interface connects the datapath with the DMA controller. It is a dual FIFO interface with a data bus
and two push lines that are used by the DMA controller to fill the FIFOs.
 The output interface is a 24-bit data bus. The configuration of this interface depends on the type of LCD
used (TFT or STN, Single or Dual Scan, 4-bit, 8-bit, 16-bit or 24-bit interface).
 The configuration interface connects the datapath with the configuration block. It is used to select between
the different datapath configurations.
 The control interface connects the datapath with the timing generation block. The main control signal is the
data-request signal, used by the timing generation module to request new data from the datapath.
The datapath can be characterized by two parameters: initial_latency and cycles_per_data. The parameter
initial_latency is defined as the number of LCDC Core Clock cycles until the first data is available at the output of
the datapath. The parameter cycles_per_data is the minimum number of LCDC Core clock cycles between two
consecutive data at the output interface.
These parameters are different for the different configurations of the LCD Controller and are shown in Table 37-2.
FIFO
Serializer
Palette
Dithering
Output
Shifter
Input Interface
Output Interface
Configuration IF
Control Interface