Datasheet

623
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
37.3 I/O Lines Description
37.4 Product Dependencies
37.4.1 I/O Lines
The pins used for interfacing the LCD Controller may be multiplexed with PIO lines. The programmer must first
program the PIO Controller to assign the pins to their peripheral function. If I/O lines of the LCD Controller are not
used by the application, they can be used for other purposes by the PIO Controller.
37.4.2 Power Management
The LCD Controller is not continuously clocked. As the LCD Controller is on the AHB bus, the clock is enabled by
setting the HCKx bit in the PMC_SCER.
37.4.3 Interrupt Sources
The LCD Controller interrupt line is connected to one of the internal sources of the Advanced Interrupt Controller.
Using the LCD Controller interrupt requires prior programming of the AIC.
37.5 Functional Description
The LCD Controller consists of two main blocks (Figure 37-1 on page 622), the DMA controller and the LCD
controller core (LCDC core). The DMA controller reads the display data from an external memory through a AHB
master interface. The LCD controller core formats the display data. The LCD controller core continuously pumps
the pixel data into the LCD module via the LCD data bus (LCDD[23:0]); this bus is timed by the LCDDOTCK,
LCDDEN, LCDHSYNC, and LCDVSYNC signals.
37.5.1 DMA Controller
37.5.1.1 Configuration Block
The configuration block is a set of programmable registers that are used to configure the DMA controller operation.
These registers are written via the AHB slave interface. Only word access is allowed.
For details on the configuration registers, see “LCD Controller (LCDC) User Interface” on page 644.
37.5.1.2 AHB Interface
This block generates the AHB transactions. It generates undefined-length incrementing bursts as well as 4- ,8- or
16-beat incrementing bursts. The size of the transfer can be configured in the BRSTLN field of the DMAFRMCFG
register. For details on this register, see “DMA Frame Configuration Register” on page 651.
Table 37-1. I/O Lines Description
Name Description Type
LCDCC Contrast control signal Output
LCDHSYNC Line synchronous signal (STN) or Horizontal synchronous signal (TFT) Output
LCDDOTCK LCD clock signal (STN/TFT) Output
LCDVSYNC Frame synchronous signal (STN) or Vertical synchronization signal (TFT) Output
LCDDEN Data enable signal Output
LCDD[23:0] LCD Data Bus output Output