Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
60
FIFO
A 45-byte FIFO is used to store data tracing. The FIFO is used to separate the pipeline status from the trace
packet, thus the FIFO can be used to buffer trace packets.
A FIFO overflow is detected by the embedded trace macrocell when the FIFO is full or when the FIFO has fewer
bytes than the user-programmed number.
Half-rate Clocking Mode
The ETM9 is implemented in half-rate mode that allows both rising and falling edge data tracing of the trace clock.
The half-rate mode is implemented to maintain the signal clock integrity of high-speed systems (up to 100 MHz).
Figure 11-5. Half-rate Clocking Mode
Care must be taken on the choice of the trace capture system as it needs to support half-rate clock functionality.
11.5.5.3 Application Board Restriction
The TCLK signal needs to be set with care, some timing parameters are required.
The specified target system connector is the AMP Mictor connector.
The connector must be oriented on the application board as shown in Figure 11-6. The view of the PCB is shown
from above with the trace connector mounted near the edge of the board. This allows the Trace Port Analyzer to
minimize the physical intrusiveness of the interconnected target.
Table 11-2. ETM Memory Map Inputs Layout
Product Resource Area Access Type Start Address End Address
SRAM Internal Data 0x0000 0000 0x002F FFFF
SRAM Internal Fetch 0x0000 0000 0x002F FFFF
ROM Internal Data 0x0040 0000 0x004F FFFF
ROM Internal Fetch 0x0040 0000 0x004F FFFF
External Bus Interface External Data 0x1000 0000 0x8FFF FFFF
External Bus Interface External Fetch 0x1000 0000 0x8FFF FFFF
User Peripherals Internal Data 0xF000 0000 0xFFFF BFFF
System Peripherals Internal Data 0xFFFF C000 0xFFFF FFFF
Half-rate Clocking Mode
Trace Clock
TraceData
ARM926EJ-S Clock