Datasheet

587
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
36.3 Block Diagram
Figure 36-1. Block Diagram
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing
8-bit values to APB registers.
The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain (MCK) and a 48
MHz clock (UDPCK) used by the 12 MHz domain.
A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE).
The external_resume signal is optional. It allows the UDP peripheral to wake up once in system mode. The host is
then notified that the device asks for a resume. This optional feature must also be negotiated with the host during
the enumeration.
36.4 Product Dependencies
For further details on the USB Device hardware implementation, see the specific Product Properties document.
The USB physical transceiver is integrated into the product. The bidirectional differential signals DP and DM are
available from the product boundary.
One I/O line may be used by the application to check that VBUS is still available from the host. Self-powered
devices may use this entry to be notified that the host has been powered off. In this case, the pullup on DP must be
disabled in order to prevent feeding current to the host. The application should disconnect the transceiver, then
remove the pullup.
36.4.1 I/O Lines
DP and DM are not controlled by any PIO controllers. The embedded USB physical transceiver is controlled by the
USB device peripheral.
To reserve an I/O line to check VBUS, the programmer must first program the PIO controller to assign this I/O in
input PIO mode.
Atmel Bridge
12 MHz
Suspend/Resume Logic
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Serial
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SIE
MCK
Master Clock
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Dual
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RAM
FIFO
UDPCK
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Domain
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USB Device
Embedded
USB
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Bus
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