Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
584
35.5 Functional Description
Please refer to the Open Host Controller Interface Specification for USB Release 1.0.a.
35.5.1 Host Controller Interface
There are two communication channels between the Host Controller and the Host Controller Driver. The first
channel uses a set of operational registers located on the USB Host Controller. The Host Controller is the target for
all communications on this channel. The operational registers contain control, status and list pointer registers.
They are mapped in the memory mapped area. Within the operational register set there is a pointer to a location in
the processor address space named the Host Controller Communication Area (HCCA). The HCCA is the second
communication channel. The host controller is the master for all communication on this channel. The HCCA
contains the head pointers to the interrupt Endpoint Descriptor lists, the head pointer to the done queue and status
information associated with start-of-frame processing.
The basic building blocks for communication across the interface are Endpoint Descriptors (ED, 4 double words)
and Transfer Descriptors (TD, 4 or 8 double words). The host controller assigns an Endpoint Descriptor to each
endpoint in the system. A queue of Transfer Descriptors is linked to the Endpoint Descriptor for the specific
endpoint.
Figure 35-2. USB Host Communication Channels
Operational
Registers
Mode
HCCA
Status
Event
Frame Int
Ratio
Control
Bulk
Host Controller
Communications Area
Interrupt 0
Interrupt 1
Interrupt 2
Interrupt 31
Done
. . .
. . .
Open HCI
Shared RAM
Device Register
in Memory Space
Device Enumeration
= Transfer Descriptor = Endpoint Descriptor
. . .