Datasheet

563
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
34.10.2 MCI Mode Register
Name: MCI_MR
Address: 0xFFFA8004
Access: Read/write
• CLKDIV: Clock Divider
Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)).
• PWSDIV: Power Saving Divider
Multimedia Card Interface clock is divided by 2
(PWSDIV)
+ 1 when entering Power Saving Mode.
Warning:
This value must be different from 0 before enabling the Power Save Mode in the MCI_CR (MCI_PWSEN bit).
• PDCPADV: PDC Padding Value
0: 0x00 value is used when padding data in write transfer (not only PDC transfer).
1: 0xFF value is used when padding data in write transfer (not only PDC transfer).
• PDCMODE: PDC-oriented Mode
0: Disables PDC transfer
1: Enables PDC transfer. In this case, UNRE and OVRE flags in the MCI Mode Register (MCI_SR) are deactivated after
the PDC transfer has been completed.
• BLKLEN: Data Block Length
This field determines the size of the data block.
Bits 16 and 17 must be set to 0
31 30 29 28 27 26 25 24
– – BLKLEN
23 22 21 20 19 18 17 16
BLKLEN 0 0
15 14 13 12 11 10 9 8
PDCMODE PDCPADV – – – PWSDIV
76543210
CLKDIV