Datasheet

53
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
10.8.1 Supported Transfers
The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight
words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that
the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests.
Table 10-7 gives an overview of the supported transfers and different kinds of transactions they are used for.
10.8.2 Thumb Instruction Fetches
All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the
ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time.
10.8.3 Address Alignment
The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary
boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word
boundaries.
Table 10-7. Supported Transfers
HBurst[2:0] Description Operation
Single Single transfer
Single transfer of word, half word, or byte:
 data write (NCNB, NCB, WT, or WB that has missed in DCache)
 data read (NCNB or NCB)
 NC instruction fetch (prefetched and non-prefetched)
 page table walk read
Incr4 Four-word incrementing burst
Half-line cache write-back, Instruction prefetch, if enabled. Four-word
burst NCNB, NCB, WT, or WB write.
Incr8 Eight-word incrementing burst Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write.
Wrap8 Eight-word wrapping burst Cache linefill