Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
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Write-back Operation
When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-
to-date with those in the external memory.
When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer
which transfers it to external memory.
10.7 Tightly-Coupled Memory Interface
10.7.1 TCM Description
The ARM926EJ-S processor features a Tightly-Coupled Memory (TCM) interface, which enables separate
instruction and data TCMs (ITCM and DTCM) to be directly reached by the processor. TCMs are used to store
real-time and performance critical code, they also provide a DMA support mechanism. Unlike AHB accesses to
external memories, accesses to TCMs are fast and deterministic and do not incur bus penalties.
The user has the possibility to independently configure each TCM size with values within the following ranges, [0
KB, 64 KB] for ITCM size and [0 KB, 64 KB] for DTCM size.
TCMs can be configured by two means: HMATRIX TCM register and TCM region register (register 9) in CP15 and
both steps should be performed. HMATRIX TCM register sets TCM size whereas TCM region register (register 9)
in CP15 maps TCMs and enables them.
The data side of the ARM9EJ-S core is able to access the ITCM. This is necessary to enable code to be loaded
into the ITCM, for SWI and emulated instruction handlers, and for accesses to PC-relative literal pools.
10.7.2 Enabling and Disabling TCMs
Prior to any enabling step, the user should configure the TCM sizes in HMATRIX TCM register. Then enabling
TCMs is performed by using TCM region register (register 9) in CP15. The user should use the same sizes as
those put in HMATRIX TCM register. For further details and programming tips, please refer to chapter 2.3 in
ARM926EJ-S TRM, ref. DDI0222B.
10.7.3 TCM Mapping
The TCMs can be located anywhere in the memory map, with a single region available for ITCM and a separate
region available for DTCM. The TCMs are physically addressed and can be placed anywhere in physical address
space. However, the base address of a TCM must be aligned to its size, and the DTCM and ITCM regions must
not overlap. TCM mapping is performed by using TCM region register (register 9) in CP15. The user should input
the right mapping address for TCMs.
10.8 Bus Interface Unit
The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU
implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between
multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix
and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture.
The multi-master bus architecture has a number of benefits:
 It allows the development of multi-master systems with an increased bus bandwidth and a flexible
architecture.
 Each AHB layer becomes simple because it only has one master, so no arbitration or master-to-slave
muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant,
nor do they have to support retry and split transactions.
 The arbitration becomes effective when more than one master wants to access the same slave
simultaneously.