Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
498
32.8.6 SSC Transmit Frame Mode Register
Name: SSC_TFMR
Address: 0xFFFBC01C (0), 0xFFFC001C (1), 0xFFFC401C (2)
Access: Read/Write
• DATLEN: Data Length
0: Forbidden value (1-bit data length not supported).
Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the
PDC2 assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15
(included), half-words are transferred, and for any other value, 32-bit words are transferred.
• DATDEF: Data Default Value
This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the
PIO Controller, the pin is enabled only if the SCC TD output is 1.
• MSBF: Most Significant Bit First
0: The lowest significant bit of the data register is shifted out first in the bit stream.
1: The most significant bit of the data register is shifted out first in the bit stream.
• DATNB: Data Number per frame
This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1).
• FSLEN: Transmit Frame Syn Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync
Data Register if FSDEN is 1.
• FSOS: Transmit Frame Sync Output Selection
31 30 29 28 27 26 25 24
–––
–
– – – FSEDGE
23 22 21 20 19 18 17 16
FSDEN FSOS FSLEN
15 14 13 12 11 10 9 8
––– – DATNB
765 4 3210
MSBF – DATDEF DATLEN
Value Selected Transmit Frame Sync Signal TF Pin
0x0 None Input-only
0x1 Negative Pulse Output
0x2 Positive Pulse Output
0x3 Driven Low during data transfer Output
0x4 Driven High during data transfer Output
0x5 Toggling at each start of data transfer Output
0x6–0x7 Reserved Undefined