Datasheet

487
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
32.6.9 Interrupt
Most bits in SSC_SR have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by
writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable
and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR
(Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected
to the AIC.
Figure 32-16. Interrupt Block Diagram
32.7 SSC Application Examples
The SSC can support several serial communication modes used in audio or high speed serial links. Some
standard applications are shown in the following figures. All serial link applications supported by the SSC are not
listed here.
Figure 32-17. Audio Application Block Diagram
SSC_IMR
PDC
Interrupt
Control
SSC Interrupt
Set
RXRDY
OVRUN
RXSYNC
Receiver
Transmitter
TXRDY
TXEMPTY
TXSYNC
TXBUFE
ENDTX
RXBUFF
ENDRX
Clear
SSC_IER
SSC_IDR
SSC
RK
RF
RD
TD
TF
TK
Clock SCK
Word Select WS
Data SD
I2S
RECEIVER
Clock SCK
Word Select WS
Data SD
Right Channel
Left Channel
MSB MSB
LSB