Datasheet

45
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
10.3.9 New ARM Instruction Set
Note: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
LDRH Load Half Word STRH Store Half Word
LDRB Load Byte STRB Store Byte
LDRBT Load Register Byte with Translation STRBT Store Register Byte with Translation
LDRT Load Register with Translation STRT Store Register with Translation
LDM Load Multiple STM Store Multiple
SWP Swap Word SWPB Swap Byte
MCR Move To Coprocessor MRC Move From Coprocessor
LDC Load To Coprocessor STC Store From Coprocessor
CDP Coprocessor Data Processing
Table 10-3. New ARM Instruction Mnemonic List
Mnemonic Operation Mnemonic Operation
BXJ Branch and exchange to Java MRRC Move double from coprocessor
BLX
(1)
Branch, Link and exchange MCR2 Alternative move of ARM reg to coprocessor
SMLAxy Signed Multiply Accumulate 16 * 16 bit MCRR Move double to coprocessor
SMLAL Signed Multiply Accumulate Long CDP2 Alternative Coprocessor Data Processing
SMLAWy Signed Multiply Accumulate 32 * 16 bit BKPT Breakpoint
SMULxy Signed Multiply 16 * 16 bit PLD
Soft Preload, Memory prepare to load from
address
SMULWy Signed Multiply 32 * 16 bit STRD Store Double
QADD Saturated Add STC2 Alternative Store from Coprocessor
QDADD Saturated Add with Double LDRD Load Double
QSUB Saturated subtract LDC2 Alternative Load to Coprocessor
QDSUB Saturated Subtract with double CLZ Count Leading Zeroes
Table 10-2. ARM Instruction Mnemonic List (Continued)
Mnemonic Operation Mnemonic Operation