Datasheet

43
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
10.3.7.2 Exceptions
Exception Types and Priorities
The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privileged mode. The types
of exceptions are:
 Fast interrupt (FIQ)
 Normal interrupt (IRQ)
 Data and Prefetched aborts (Abort)
 Undefined instruction (Undefined)
 Software interrupt and Reset (Supervisor)
When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the
state.
More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen exceptions according to
the following priority order:
 Reset (highest priority)
 Data Abort
 FIQ
 IRQ
 Prefetch Abort
 BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority)
The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive.
There is one exception in the priority scheme though, when FIQs are enabled and a Data Abort occurs at the same
time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A
normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher
priority than FIQs to ensure that the transfer error does not escape detection.
Exception Modes and Handling
Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an
interrupt from a peripheral.
When handling an ARM exception, the ARM9EJ-S core performs the following operations:
1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new
mode that has been entered. When the exception entry is from:
 ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current
PC(r15) + 4 or PC + 8 depending on the exception).
 THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC
+ 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place
on return.
2. Copies the CPSR into the appropriate SPSR.
3. Forces the CPSR mode bits to a value that depends on the exception.
4. Forces the PC to fetch the next instruction from the relevant exception vector.
The register r13 is also banked across exception modes to provide each exception handler with private stack
pointer.
The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions.
When an exception has completed, the exception handler must move both the return value in the banked LR
minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception.
This action restores both PC and the CPSR.