Datasheet

SAM9261 [DATASHEET]

Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16

404

Figure 30-19. TWI Read Operation with Single Data Byte and Internal Address

Set the Control register:

- Master enable

TWI_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address

- Internal address size (IADRSZ)

- Transfer direction bit

Read ==> bit MREAD = 1

Read Status register

TXCOMP = 1?

END

BEGIN

Ye s

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Ye s

Set the internal address

TWI_IADR = address

Start the transfer

TWI_CR = START | STOP

Read Status register

RXRDY = 1?

Read Receive Holding register