Datasheet

391
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
30. Two Wire Interface (TWI)
30.1 Overview
The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock
line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can
be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time
Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is
programmable as a master or a slave with sequential or single-byte access. Multiple master capability is
supported. Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus
arbitration is lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock
frequencies.
Table 30-1 below lists the compatibility level of the Atmel Two-wire Interface in Master Mode and a full
I2C compatible device.
Note: 1. START + b000000001 + Ack + Sr
30.2 Embedded Characteristics
 Compatibility with standard two-wire serial memory
 One, two or three bytes for slave address
 Sequential read/write operations
Table 30-1. Atmel TWI compatibility with i2C Standard
I2C Standard Atmel TWI
Standard Mode Speed (100 KHz) Supported
Fast Mode Speed (400 KHz) Supported
7 or 10 bits Slave Addressing Supported
START BYTE
(1)
Not Supported
Repeated Start (Sr) Condition Supported
ACK and NACK Management Supported
Slope control and input filtering (Fast mode) Not Supported
Clock stretching Supported