Datasheet

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SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
10.2 Block Diagram
Figure 10-1. ARM926EJ-S Internal Functional Block Diagram
10.3 ARM9EJ-S Processor
10.3.1 ARM9EJ-S Operating States
The ARM9EJ-S processor can operate in three different states, each with a specific instruction set:
 ARM state: 32-bit, word-aligned ARM instructions.
 Thumb state: 16-bit, halfword-aligned Thumb instructions.
 Jazelle state: variable length, byte-aligned Jazelle instructions.
In Jazelle state, all instruction Fetches are in words.
10.3.2 Switching State
The operating state of the ARM9EJ-S core can be switched between:
 ARM state and Thumb state using the BX and BLX instructions, and loads to the PC
 ARM state and Jazelle state using the BXJ instruction
ARM9EJ-S
ICE
Interface
ARM926EJ-S
EmbeddedICE
-RT
Processor
ETM
Interface
Coprocessor
Interface
Droute
Iroute
IEXT
ICACHE
MMU
DCACHE
DEXT
IA
TCM
Interface
Bus
Interface
Unit
AHB
AHB
Data
AHB
Interface
Instruction
AHB
Interface
INSTR
R DATAW DATA
DA