Datasheet

37
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
9.10 Synchronous Serial Controller
 Provides serial synchronous communication links used in audio and telecom applications (with CODECs in
Master or Slave Modes, I
2
S, TDM Buses, Magnetic Card Reader and more).
 Contains an independent receiver and transmitter and a common clock divider.
 Offers a configurable frame sync and data length.
 Receiver and transmitter can be programmed to start automatically or on detection of different event on the
frame sync signal.
 Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal.
9.11 Timer Counter
See Section 33.2 “Embedded Characteristics”.
9.12 Multimedia Card Interface
See Section 34.2 “Embedded Characteristics”.
9.13 USB
 USB Host Port
 See Section 35.2 “Embedded Characteristics”.
 USB Device Port
 Six general-purpose endpoints:
 Endpoint 0: 8 bytes, no ping-pong mode
 Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode
 Endpoint 3: 64 bytes, no ping-pong mode
 Endpoint 4, Endpoint 5: 256 bytes, ping-pong mode
 See Section 36.2 “Embedded Characteristics”.
 Embedded pad pull-up configurable via USB_PUCR located in the MATRIX user interface
9.14 LCD Controller
 Single and Dual scan color and monochrome passive STN LCD panels supported
 Single scan active TFT LCD panels supported.
 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported
 Up to 24-bit single scan TFT interfaces supported
 Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays
 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN
 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN
 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT
 Single clock domain architecture
 Resolution supported up to 2048 x 2048