Datasheet

301
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
27. Debug Unit (DBGU)
27.1 Overview
The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s
ARM-based systems.
The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an
ideal medium for in-situ programming solutions and debug monitor communications. The Debug Unit two-pin
UART can be used stand-alone for general purpose serial communication. Moreover, the association with two
peripheral data controller channels permits packet handling for these tasks with processor time reduced to a
minimum.
The Debug Unit also makes the Debug Communication Channel (DCC) signals provided by the In-circuit Emulator
of the ARM processor visible to the software. These signals indicate the status of the DCC read and write registers
and generate an interrupt to the ARM processor, making possible the handling of the DCC under interrupt control.
Chip Identifier registers permit recognition of the device and its revision. These registers inform as to the sizes and
types of the on-chip memories, as well as the set of embedded peripherals.
Finally, the Debug Unit features a Force NTRST capability that enables the software to decide whether to prevent
access to the system via the In-circuit Emulator. This permits protection of the code, stored in ROM.
27.2 Embedded Characteristics
 Composed of four functions
 Two-pin UART
 Debug Communication Channel (DCC) support
 Chip ID Registers
 ICE Access Prevention
 Two-pin UART
 Implemented features are 100% compatible with the standard Atmel USART
 Independent receiver and transmitter with a common programmable Baud Rate Generator
 Even, Odd, Mark or Space Parity Generation
 Parity, Framing and Overrun Error Detection
 Automatic Echo, Local Loopback and Remote Loopback Channel Modes
 Support for two PDC channels with connection to receiver and transmitter
 Debug Communication Channel Support
 Offers visibility of COMMRX and COMMTX signals from the ARM Processor
 Chip ID Registers
 Identification of the device revision, sizes of the embedded memories, set of peripherals
 ICE Access prevention
 Enables software to prevent system access through the ARM Processor’s ICE
 Prevention is made by asserting the NTRST line of the ARM Processor’s ICE