Datasheet

SAM9261 [DATASHEET]

Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16

9.3 Peripheral Multiplexing on PIO Lines

The SAM9261 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral

set.

Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two peripheral functions, A

or B. The tables in Section 9.3.2 “PIO Controller Multiplexing Tables”

define how the I/O lines of the peripherals A

and B are multiplexed on the PIO Controllers. The tables include the columns “Function” and “Comments” which

can be used by the user to track how pins are defined in an application.

Note that some output only peripheral functions might be duplicated within the tables.

The column “Reset State” indicates whether the PIO line resets in I/O mode or in peripheral mode. If I/O is

mentioned, the PIO line resets in input with the pull-up enabled, so that the device is maintained in a static state as

soon as the reset is released. As a result, the bit corresponding to the PIO line in the Peripheral Status Register

(PIO_PSR) resets low.

If a signal name is mentioned in the “Reset State” column, the PIO line is assigned to this function and the

corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address

lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also

enabled in this case.

9.3.1 Resource Multiplexing

9.3.1.1 LCD Controller

The LCD Controller can interface with several LCD panels. It supports 4, 8 or 16 bit-per-pixel without any limitation.

Interfacing 24 bit-per-pixel TFTs panel prevents using the SSC0 and the chip select line 0 of the SPI1.

16 bit-per-pixel TFT panels are interfaced through peripheral B functions, as color data is output on LCDD3 to

LCDD7, LCDD11 to LCDD15 and LCDD19 to LCDD23. Intensity bit is output on LCDD2, LCDD10 and LCDD18.

Using the peripheral B does not prevent using the SSC0 and the SPI1 lines.

9.3.1.2 ETM

Using the ETM prevents:

 using the USART1 and USART2 control signals, in particular the SCK lines which are required to use the

USART as ISO7816 and the RTS and CTS to handle hardware handshaking on the serial lines. In case the

ETM and an ISO7816 connection are both required, the USART0 has to be used as a Smart Card interface.

 using the SSC1

 addressing a static memory of more than 8 Mbytes, which requires the A23 and A24 address lines

 using the chip select lines 1 to 3 of SPI0 and SPI1

9.3.1.3 EBI

If not required, the NWAIT function (external wait request) can be deactivated by software, allowing this pin to be

used as a PIO.

9.3.1.4 32-bit Data Bus

Using a 32-bit Data Bus prevents:

 using the three Timer Counter channels’ outputs and trigger inputs

 using the SSC2

9.3.1.5 NAND Flash Interface

Using the NAND Flash interface prevents:

 using NCS3, NCS6 and NCS7 to access other parallel devices