Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
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26.8 Advanced Interrupt Controller (AIC) User Interface
26.8.1 Base Address
The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring fea-
ture, as the PC-relative load/store instructions of the ARM processor support only a ± 4-Kbyte offset.
Notes: 1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset,
thus not pending.
2. PID2...PID31 bit fields refer to the identifiers as defined in the Peripheral Identifiers section of the product datasheet.
Table 26-2. Register Mapping
Offset Register Name Access Reset
0x00 Source Mode Register 0 AIC_SMR0 Read/Write 0x0
0x04 Source Mode Register 1 AIC_SMR1 Read/Write 0x0
... ... ... ... ...
0x7C Source Mode Register 31 AIC_SMR31 Read/Write 0x0
0x80 Source Vector Register 0 AIC_SVR0 Read/Write 0x0
0x84 Source Vector Register 1 AIC_SVR1 Read/Write 0x0
... ... ... ... ...
0xFC Source Vector Register 31 AIC_SVR31 Read/Write 0x0
0x100 Interrupt Vector Register AIC_IVR Read-only 0x0
0x104 FIQ Interrupt Vector Register AIC_FVR Read-only 0x0
0x108 Interrupt Status Register AIC_ISR Read-only 0x0
0x10C Interrupt Pending Register
(2)
AIC_IPR Read-only 0x0
(1)
0x110 Interrupt Mask Register
(2)
AIC_IMR Read-only 0x0
0x114 Core Interrupt Status Register AIC_CISR Read-only 0x0
0x118–0x11C Reserved – – –
0x120 Interrupt Enable Command Register
(2)
AIC_IECR Write-only –
0x124 Interrupt Disable Command Register
(2)
AIC_IDCR Write-only –
0x128 Interrupt Clear Command Register
(2)
AIC_ICCR Write-only –
0x12C Interrupt Set Command Register
(2)
AIC_ISCR Write-only –
0x130 End of Interrupt Command Register AIC_EOICR Write-only –
0x134 Spurious Interrupt Vector Register AIC_SPU Read/Write 0x0
0x138 Debug Control Register AIC_DCR Read/Write 0x0
0x13C Reserved – – –
0x140 Fast Forcing Enable Register
(2)
AIC_FFER Write-only –
0x144 Fast Forcing Disable Register
(2)
AIC_FFDR Write-only –
0x148 Fast Forcing Status Register
(2)
AIC_FFSR Read-only 0x0
0x14C–0x1E0 Reserved – – –
0x1EC–0x1FC Reserved – – –