Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
274
26.7.1.4 Interrupt Status
For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its mask in AIC_IMR
(Interrupt Mask Register). AIC_IPR enables the actual activity of the sources, whether masked or not.
The AIC_ISR reads the number of the current interrupt (see “Priority Controller” on page 276) and the register
AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor.
Each status referred to above can be used to optimize the interrupt handling of the systems.
26.7.1.5 Internal Interrupt Source Input Stage
Figure 26-4. Internal Interrupt Source Input Stage
26.7.1.6 External Interrupt Source Input Stage
Figure 26-5. External Interrupt Source Input Stage
26.7.2 Interrupt Latencies
Global interrupt latencies depend on several parameters, including:
 The time the software masks the interrupts.
 Occurrence, either at the processor level or at the AIC level.
 The execution time of the instruction in progress when the interrupt occurs.
 The treatment of higher priority interrupts and the resynchronization of the hardware signals.
Edge
Detector
ClearSet
Source i
AIC_IPR
AIC_IMR
AIC_IECR
AIC_IDCR
AIC_ISCR
AIC_ICCR
Fast Interrupt Controller
or
Priority Controller
FF
Lev
el/
Edge
AIC_SMRI
(SRCTYPE)
Edge
Detector
ClearSet
Pos./Neg.
AIC_ISCR
AIC_ICCR
Source i
FF
Level/
Edge
High/Low
AIC_SMRi
SRCTYPE
AIC_IPR
AIC_IMR
AIC_IECR
AIC_IDCR
Fast Interrupt Controller
or
Priority Controller