Datasheet

273
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
the interrupt. This is performed by reading successively the status registers of the above mentioned system
peripherals.
The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to
external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller.
The PIO Controllers are considered as user peripherals in the scope of interrupt handling. Accordingly, the PIO
Controller interrupt lines are connected to the Interrupt Sources 2 to 31.
The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the
bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional
operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31.
26.7 Functional Description
26.7.1 Interrupt Source Control
26.7.1.1 Interrupt Source Mode
The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the
corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source.
The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed
either in level-sensitive mode or in edge-triggered mode. The active level of the internal interrupts is not important
for the user.
The external interrupt sources can be programmed either in high level-sensitive or low level-sensitive modes, or in
positive edge-triggered or negative edge-triggered modes.
26.7.1.2 Interrupt Source Enabling
Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers;
AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register). This set
of registers conducts enabling or disabling in one instruction. The interrupt mask can be read in the AIC_IMR. A
disabled interrupt does not affect servicing of other interrupts.
26.7.1.3 Interrupt Clearing and Setting
All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or
cleared by writing respectively the AIC_ISCR and AIC_ICCRs. Clearing or setting interrupt sources programmed
in level-sensitive mode has no effect.
The clear operation is perfunctory, as the software must perform an action to reinitialize the “memorization”
circuitry activated when the source is programmed in edge-triggered mode. However, the set operation is available
for auto-test or software debug purposes. It can also be used to execute an AIC-implementation of a software
interrupt.
The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector Register) is read.
Only the interrupt source being detected by the AIC as the current interrupt is affected by this operation. (See
“Priority Controller” on page 276.) The automatic clear reduces the operations required by the interrupt service
routine entry code to reading the AIC_IVR. Note that the automatic interrupt clear is disabled if the interrupt source
has the Fast Forcing feature enabled as it is considered uniquely as a FIQ source. (For further details, See “Fast
Forcing” on page 279.)
The automatic clear of the interrupt source 0 is performed when AIC_FVR is read.