Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
272
26.4 AIC Detailed Block Diagram
Figure 26-3. AIC Detailed Block Diagram
26.5 I/O Line Description
26.6 Product Dependencies
26.6.1 I/O Lines
The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on
the features of the PIO controller used in the product, the pins must be programmed in accordance with their
assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the
input path.
26.6.2 Power Management
The Advanced Interrupt Controller is continuously clocked. The Power Management Controller has no effect on
the Advanced Interrupt Controller behavior.
The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the ARM processor
while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without
asserting the interrupt line of the processor, thus providing synchronization of the processor on an event.
26.6.3 Interrupt Sources
The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the Interrupt Source 0
cannot be used.
The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system
peripheral interrupt lines. When a system interrupt occurs, the service routine must first distinguish the cause of
FIQ
PIO
Controller
Advanced Interrupt Controller
IRQ0-IRQn
PIOIRQ
Embedded
Peripherals
External
Source
Input
Stage
Internal
Source
Input
Stage
Fast
Forcing
Interrupt
Priority
Controller
Fast
Interrupt
Controller
ARM
Processor
nFIQ
nIRQ
Power
Management
Controller
Wake UpUser Interface
APB
Processor
Clock
Table 26-1. I/O Line Description
Pin Name Pin Description Type
FIQ Fast Interrupt Input
IRQ0–IRQn Interrupt 0–Interrupt n Input