Datasheet
27
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
8.10 Advanced Interrupt Controller
Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor
Thirty-two individually maskable and vectored interrupt sources
Source 0 is reserved for the Fast Interrupt Input (FIQ)
Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
Source 2 to Source 31 control up to thirty embedded peripheral interrupts or external interrupts
Programmable edge-triggered or level-sensitive internal sources
Programmable positive/negative edge-triggered or high/low level-sensitive
Four External Sources
8-level Priority Controller
Drives the normal interrupt of the processor
Handles priority of the interrupt sources 1 to 31
Higher priority interrupts can be served during service of lower priority interrupt
Vectoring
Optimizes Interrupt Service Routine Branch and Execution
One 32-bit Vector Register per interrupt source
Interrupt Vector Register reads the corresponding current Interrupt Vector
Protect Mode
Easy debugging by preventing automatic operations when protect mode is enabled
Fast Forcing
Permits redirecting any normal interrupt source on the Fast Interrupt of the processor
General Interrupt Mask
Provides processor synchronization on events without triggering an interrupt
8.11 Debug Unit
See Section 27.2 “Embedded Characteristics”.
8.12 PIO Controllers
Three PIO Controllers, each controlling up to 32 programmable I/O Lines
PIOA has 32 I/O Lines
PIOB has 32 I/O Lines
PIOC has 32 I/O Lines
Fully programmable through Set/Clear Registers
Multiplexing of two peripheral functions per I/O Line
For each I/O Line (whether assigned to a peripheral or used as general-purpose I/O)
Input change interrupt
Glitch filter
Multi-drive option enables driving in open drain
Programmable pull up on each I/O line
Pin data status register, supplies visibility of the level on the pin at any time
Synchronous output, provides Set and Clear of several I/O lines in a single write