Datasheet

263
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
25. Watchdog Timer (WDT)
25.1 Overview
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It
features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It
can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in
debug mode or idle mode.
25.2 Embedded Characteristics
 12-bit key-protected only-once programmable counter
 Windowed, prevents the processor to be in a dead-lock on the watchdog access
25.3 Block Diagram
Figure 25-1. Watchdog Timer Block Diagram
=
0
10
set
reset
read WDT_SR
or
reset
wdt_fault
(to Reset Controlle
r)
set
reset
WDFIEN
wdt_int
WDT_MR
SLCK
1/128
12-bit Down
Counter
Current
Value
WDD
WDT_MR
<= WDD
WDV
WDRSTT
WDT_MR
WDT_CR
reload
WDUNF
WDERR
reload
write WDT_MR
WDRSTEN
WDT_MR