Datasheet

25
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
8.2 Reset Controller
See Section 13.2 “Embedded Characteristics”.
8.3 Shutdown Controller
See Section 16.2 “Embedded Characteristics”.
8.4 General-purpose Backup Registers
 Four 32-bit general-purpose backup registers
8.5 Clock Generator
 Embeds the Low-power 32.768 kHz Slow Clock Oscillator
 Provides the permanent Slow Clock to the system
 Embeds the Main Oscillator
 Oscillator bypass feature
 Supports 3 to 20 MHz crystals
 Embeds Two PLLs
 Outputs 80 to 240 MHz clocks
 Integrates an input divider to increase output accuracy
 1 MHz minimum input frequency
 Provides SLCK, MAINCK, PLLACK and PLLBCK.
Figure 8-2. Clock Generator Block Diagram
Power
Management
Controller
XIN
XOUT
PLLRCA
Slow Clock
SLCK
Main Clock
MAINCK
PLLA Clock
PLLACK
ControlStatus
PLL and
Divider B
PLLRCB
PLLB Clock
PLLBCK
XIN32
XOUT32
Slow Clock
Oscillator
Main
Oscillator
PLL and
Divider A
Clock Generator