Datasheet

239
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
The MDIV field is used to control the Master Clock divider. It is possible to choose between different values
(0, 1, 2). The Master Clock output is Processor Clock divided by 1, 2 or 4, depending on the value
programmed in MDIV. By default, MDIV is set to 0, which indicates that the Processor Clock is equal to the
Master Clock.
Once the PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR.
This can be done either by polling the status register or by waiting for the interrupt line to be raised if the
associated interrupt to MCKRDY has been enabled in the PMC_IER.
The PMC_MCKR must not be programmed in a single write operation. For each clock switching, the user
must take care to:
 change one by one the CSS, MDIV, and PRES fields
 wait till the MCKRDY bit is set in PMC_SR before changing the PMC_MCKR
 ensure that each transitory frequency value is in the operational range for PCK and MCK.
If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit will go low to
indicate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY
bit to be set again before using the Master and Processor Clocks.
Note: IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR
(CKGR_PLLAR or CKGR_PLLBR), the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again,
LOCK (LOCKA or LOCKB) goes high and MCKRDY is set.
While PLLA is unlocked, the Master Clock selection is automatically changed to Slow Clock. While PLLB is unlocked,
the Master Clock selection is automatically changed to Main Clock. For further information, see Section 24.8.2. “Clock
Switching Waveforms” on page 242.
Code Example:
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)
wait (MCKRDY=1)
The Master Clock is main clock divided by 16.
The Processor Clock is the Master Clock.
6. Selection of Programmable clocks
Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR.
Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDRs. Depending
on the system used, 4 Programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear
indication as to which Programmable clock is enabled. By default all Programmable clocks are disabled.
PMC_PCKx registers are used to configure Programmable clocks.
The CSS field is used to select the Programmable clock divider source. Four clock options are available:
main clock, slow clock, PLLACK, PLLBCK. By default, the clock source selected is slow clock.
The PRES field is used to control the Programmable clock prescaler. It is possible to choose between
different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES
parameter. By default, the PRES parameter is set to 0 which means that master clock is equal to slow clock.
Once the PMC_PCKx register has been programmed, The corresponding Programmable clock must be
enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR. This can be done
either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to