Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
238
The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in the PMC_SR
after CKGR_PLLAR has been written.
Once CKGR_PLLAR has been written, the user is obliged to wait for the LOCKA bit to be set in the
PMC_SR. This can be done either by polling the status register or by waiting the interrupt line to be raised if
the associated interrupt to LOCKA has been enabled in the PMC_IER.
All parameters in CKGR_PLLAR can be programmed in a single write operation. If at some stage one of the
following parameters, SRCA, MULA, DIVA is modified, LOCKA bit will go low to indicate that PLL A is not
ready yet. When PLL A is locked, LOCKA will be set again. User has to wait for LOCKA bit to be set before
using the PLL A output clock.
Code Example:
write_register(CKGR_PLLAR,0x20030605)
PLL A and divider A are enabled. PLL A input clock is main clock divided by 5. PLL An output clock is PLL A
input clock multiplied by 4. Once CKGR_PLLAR has been written, LOCKA bit will be set after six slow clock
cycles.
4. Setting PLL B and divider B:
All parameters needed to configure PLL B and divider B are located in the CKGR_PLLBR. ICPPLLB in
PMC_PLLICPR must be set to 1 before configuring the CKGR_PLLBR.
The DIVB field is used to control divider B itself. A value between 0 and 255 can be programmed. Divider B
output is divider B input divided by DIVB parameter. By default DIVB parameter is set to 0 which means that
divider B is turned off.
The OUTB field is used to select the PLL B output frequency range.
The MULB field is the PLL B multiplier factor. This parameter can be programmed between 0 and 2047. If
MULB is set to 0, PLL B will be turned off, otherwise the PLL B output frequency is PLL B input frequency
multiplied by (MULB + 1).
The PLLBCOUNT field specifies the number of slow clock cycles before LOCKB bit is set in the PMC_SR
after CKGR_PLLBR has been written.
Once the PMC_PLLB register has been written, the user must wait for the LOCKB bit to be set in the
PMC_SR. This can be done either by polling the status register or by waiting the interrupt line to be raised if
the associated interrupt to LOCKB has been enabled in the PMC_IER. All parameters in CKGR_PLLBR can
be programmed in a single write operation. If at some stage one of the following parameters, MULB, DIVB is
modified, LOCKB bit will go low to indicate that PLL B is not ready yet. When PLL B is locked, LOCKB will be
set again. The user is constrained to wait for LOCKB bit to be set before using the PLL A output clock.
The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the USB clock(s).
Code Example:
write_register(CKGR_PLLBR,0x00040805)
If PLL B and divider B are enabled, the PLL B input clock is the main clock. PLL B output clock is PLL B input
clock multiplied by 5. Once CKGR_PLLBR has been written, LOCKB bit will be set after eight slow clock
cycles.
5. Selection of Master Clock and Processor Clock
The Master Clock and the Processor Clock are configurable via the PMC_MCKR.
The CSS field is used to select the Master Clock divider source. By default, the selected clock source is slow
clock.
The PRES field is used to control the Master Clock prescaler. The user can choose between different values
(1, 2, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by PRES parameter. By default, PRES
parameter is set to 0 which means that master clock is equal to slow clock.