Datasheet

231
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
23. Clock Generator (CKGR)
23.1 Overview
The Clock Generator is made up of 2 PLL, a Main Oscillator, and a 32.768 kHz low-power Oscillator.
It provides the following clocks:
 SLCK, the Slow Clock, which is the only permanent clock within the system
 MAINCK is the output of the Main Oscillator
The Clock Generator User Interface is embedded within the Power Management Controller one and is described
in Section 24.9. However, the Clock Generator registers are named CKGR_.
 PLLACK is the output of the Divider and PLL A block
 PLLBCK is the output of the Divider and PLL B block
23.2 Slow Clock Crystal Oscillator
The Clock Generator integrates a 32.768 kHz low-power oscillator. The XIN32 and XOUT32 pins must be
connected to a 32.768 kHz crystal. Two external capacitors must be wired as shown in Figure 23-1.
Figure 23-1. Typical Slow Clock Crystal Oscillator Connection
23.3 Main Oscillator
Figure 23-2 shows the Main Oscillator block diagram.
Figure 23-2. Main Oscillator Block Diagram
XIN32 XOUT32 GNDBU
32,768 Hz
Crystal
XIN
XOUT
MOSCEN
Main
Oscillator
Counter
OSCOUNT
MOSCS
MAINCK
Main Clock
Main Clock
Frequency
Counter
MAINF
MAINRDY
SLCK
Slow Clock
Main
Oscillator