Datasheet

21
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory.
This is done via hardware at reset.
Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the
complete memory map presented in Figure 7-1 on page 17.
The SAM9261 Bus Matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal
memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus
Interface.
7.1.2.1 BMS = 1, Boot on Embedded ROM
The system boots using the Boot Program.
 Enable the 32.768 kHz oscillator
 Auto baud rate detection
 Downloads and runs an application from external storage media into internal SRAM
 Automatic detection of valid application
 Bootloader on a non-volatile memory
 SPI Serial Flash or DataFlash connected on NPCS0 of SPI0
 NAND Flash
 SDCard (boot ROM does not support high-capacity SDCards)
 SAM-BA
®
boot in case no valid program is detected in external NVM, supporting:
 Serial Communication on a DBGU
 USB Device HS Port
7.1.2.2 BMS = 0, Boot on External Memory
 Boot on slow clock (32.768 kHz)
 Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus,
Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS = 0), the user must take the following
steps:
1. Program the PMC (main oscillator enable or bypass mode).
2. Program and start the PLL.
3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock
4. Switch the main clock to the new value.
7.1.3 ETM Memories
The eight ETM9 Medium+ memory map decoder inputs are connected to custom address decoders and the
resulting memory mapping is summarized in Table 7-6 on page 22.