Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
208
21.6.3 SDRAMC Configuration Register
Register: SDRAMC_CR
Address: 0xFFFFEA08
Access: Read/Write
• NC: Number of Column Bits
Reset value is 8 column bits.
• NR: Number of Row Bits
Reset value is 11 row bits.
• NB: Number of Banks
Reset value is two banks.
31 30 29 28 27 26 25 24
TXSR TRAS
23 22 21 20 19 18 17 16
TRCD TRP
15 14 13 12 11 10 9 8
TRC TWR
76543210
DBW CAS NB NR NC
Value Column Bits
00 8
01 9
10 10
11 11
Value Row Bits
00 11
01 12
10 13
11 Reserved
Value Number of Banks
02
14