Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
202
21.5.5 Power Management
Three low-power modes are available:
 Self-refresh Mode: The SDRAM executes its own Auto-refresh cycle without control of the SDRAM
Controller. Current drained by the SDRAM is very low.
 Powerdown Mode: Auto-refresh cycles are controlled by the SDRAM Controller. Between auto-refresh
cycles, the SDRAM is in powerdown. Current drained in Powerdown mode is higher than in Self-refresh
Mode.
 Deep Powerdown Mode: (Only available with Mobile SDRAM) The SDRAM contents are lost, but the
SDRAM does not drain any current.
The SDRAM Controller activates one low-power mode as soon as the SDRAM device is not selected. It is possible
to delay the entry in self-refresh and powerdown mode after the last access by programming a timeout value in the
Low Power Register.
21.5.5.1 Self-refresh Mode
This mode is selected by programming the LPCB field to 1 in the SDRAMC Low Power Register. In self-refresh
mode, the SDRAM device retains data without external clocking and provides its own internal clocking, thus
performing its own auto-refresh cycles. All the inputs to the SDRAM device become “don’t care” except SDCKE,
which remains low. As soon as the SDRAM device is selected, the SDRAM Controller provides a sequence of
commands and exits self-refresh mode.
Some low-power SDRAMs (e.g., mobile SDRAM) can refresh only one quarter or a half quarter or all banks of the
SDRAM array. This feature reduces the self-refresh current. To configure this feature, Temperature Compensated
Self Refresh (TCSR), Partial Array Self Refresh (PASR) and Drive Strength (DS) parameters must be set in the
Low Power Register and transmitted to the low-power SDRAM during initialization.
The SDRAM device must remain in self-refresh mode for a minimum period of t
RAS
and may remain in self-refresh
mode for an indefinite period. This is described in Figure 21-6.
Figure 21-6. Self-refresh Mode Behavior
SDCK
SDCS
RAS
CAS
SDRAMC_A[12:0]
Self Refresh Mode
SDWE
Row
T
XSR
= 3
SDCKE
Write
SDRAMC_SRR
SRCB = 1
Access Request
to the SDRAM Controller