Datasheet

201
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
21.5.4 SDRAM Controller Refresh Cycles
An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by
the SDRAM device and incremented after each auto-refresh automatically. The SDRAM Controller generates
these auto-refresh commands periodically. An internal timer is loaded with the value in the register SDRAMC_TR
that indicates the number of clock cycles between refresh cycles.
A refresh error interrupt is generated when the previous auto-refresh command did not perform. It is acknowledged
by reading the Interrupt Status Register (SDRAMC_ISR).
When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses are not delayed.
However, if the CPU tries to access the SDRAM, the slave indicates that the device is busy and the master is held
by a wait signal. See Figure 21-5.
Figure 21-5. Refresh Cycle Followed by a Read Access
SDCK
SDCS
RAS
CAS
SDRAMC_A[12:0]
D[31:0]
(input)
t
RP
= 3
SDWE
Dnb
Dnc
Dnd
col c col d
CAS = 2
Row m
col a
t
RC
= 8 t
RCD
= 3
Dma
Row n