Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
20
Note: 1. Configuration after reset.
7.1.1.2 Internal ROM
The SAM9261 integrates a 32 Kbyte Internal ROM mapped at address 0x0040 0000. It is also accessible at
address 0x0 after reset and before remap if the BMS is tied high during reset.
7.1.1.3 USB Host Port
The SAM9261 integrates a USB Host Port Open Host Controller Interface (OHCI). The registers of this interface
are directly accessible on the AHB Bus and are mapped like a standard internal memory at address 0x0050 0000.
7.1.1.4 LCD Controller
The SAM9261 integrates an LCD Controller. The interface is directly accessible on the AHB Bus and is mapped
like a standard internal memory at address 0x0060 0000.
7.1.2 Boot Strategies
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory
layout can be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by
software once the system has booted for each Master of the Bus Matrix. Refer to Section 18. “Bus Matrix” for more
details.
Table 7-5. 16 Kbyte Block Allocation
Decoded
Area Address
Configuration Examples and Related 16 Kbyte Block Assignments
ITCM = 0 Kbyte
DTCM = 0 Kbyte
AHB = 160 Kbytes
(1)
ITCM = 64 Kbytes
DTCM = 64 Kbytes
AHB = 32 Kbytes
ITCM = 32 Kbytes
DTCM = 64 Kbytes
AHB = 64 Kbytes
ITCM = 32 Kbytes
DTCM = 16 Kbytes
AHB = 112 Kbytes
Internal
SRAM A
(ITCM)
0x0010 0000 – RB3 RB3 RB3
0x0010 4000 – RB2 RB2 RB2
0x0010 8000 – RB1 – –
0x0010 C000 – RB0 – –
Internal
SRAM B
(DTCM)
0x0020 0000 – RB7 RB7 RB7
0x0020 4000 – RB6 RB6 –
0x0020 8000 – RB5 RB5 –
0x0020 C000 – RB4 RB4 –
Internal
SRAM C
(AHB)
0x0030 0000 RB9 RB9 RB9 RB9
0x0030 4000 RB8 RB8 RB8 RB8
0x0030 8000 RB7 – RB1 RB6
0x0030 C000 RB6 – RB0 RB5
0x0031 0000 RB5 – – RB4
0x0031 4000 RB4 – – RB1
0x0031 8000 RB3 – – RB0
0x0031 C000 RB2 – – –
0x0032 0000 RB1 – – –
0x0032 4000 RB0 – – –